1. Field of the Invention
The present invention relates to nonvolatile semiconductor memory devices, and more particularly to a NOR-type flash memory device and a verify method thereof.
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional NOR-type flash memory device. FIG. 2 is a circuit diagram showing more details of the word line voltage supplying circuit of FIG. 1 along with a row selector and a word line voltage supplying circuit associated with a memory cell.
Referring to FIG. 1, the flash memory device includes a memory cell array 10 which, although not shown, has a plurality of word lines, a plurality of bit lines and a plurality of memory cells arranged at intersections of the word lines and the bit lines. Each of the memory cells has a control gate connected to a corresponding word line, a floating gate, a source grounded, and a drain connected to a corresponding bit line, as illustrated in FIG. 2. FIG. 3 is a sectional diagram of the memory cell shown in FIG. 2.
Referring again to FIG. 1, at the left side of the array 10 is a row selector 20 which selects the word lines in accordance with a row address from the address buffer 30. As illustrated in FIG. 2, the row selector 20 includes one NAND gate G1 which receives decoded row address signals DRAi, one invertor INV1 and one level shifter LS1 connected as illustrated in FIG. 2. The row selector 20 selects one of the word lines in response to the decoded row address signals DRAi, and then drives the selected word line with a word line voltage signal from a word line voltage supplying circuit 50.
The word line voltage supplying circuit 50 includes a high voltage generator 52, a voltage regulator 54, and a switching circuit 56. The high voltage generator 52 produces a high voltage signal VPI (for example, 10V) in response to a verify enable signal VE.sub.-- EN during a verify operation. The high voltage generator 52 can be realized by use of a charge pumping circuit as is well known in the art. The voltage regulator 54 controls the level of the high voltage signal VPI to provide a voltage signal VPP which is required for various verify modes of operation. The voltage regulator 54 can be realized using resistive or capacitive dividing techniques which are well known.
The switching circuit 56 includes two level shifters LS2 and LS3, and two PMOS transistors MP1 and MP2 connected as illustrated in FIG. 2. The switching circuit 56 transfers either the power supply voltage VCC or the voltage VPP from the voltage regulator 54 to the row selector 20 in response to the verify enable signal VE.sub.-- EN. For instance, when the signal VE.sub.-- EN is at a logic low level, the PMOS transistor MP1 is turned off and the PMOS transistor MP2 is turned on, so that the power supply voltage VCC is transferred to the row selector 20 as a word line voltage. When the signal VE.sub.-- EN is at a logic high level, the PMOS transistor MP1 is turned on and the PMOS transistor MP2 is turned off, so that the voltage VPP is transferred to the row selector 20 as the word line voltage.
Referring again to FIG. 1, the flash memory device further includes a sense amplifier circuit 60, an input/output buffer circuit 70 and a control logic and command register 80. The address buffer circuit 30, the column selector 40, the sense amplifier circuit 60 and the input/output buffer circuit 70 are controlled by the control logic and command register 80. Each of the memory cells is programmed by applying a high voltage of, for example, 10V to the control gate, a low voltage such as the ground voltage to the source and the bulk, and a voltage of, for example, 5V to 6V to the drain. The programmed memory cells are referred to as "OFF cells", and have a threshold voltage distribution of 6V through 7V, respectively. The memory cells of the array 10 are simultaneously erased by applying a negative high voltage of, for example, -10V, to the control gates and a voltage of, for example, 5V, to the bulk and by allowing the drains and the sources to float. The erased memory cells are referred to as "ON cells", and have a threshold voltage distribution of 1V through 3V, respectively. Threshold voltages distribution associated with OFF cells and ON cells are shown in FIG. 4.
In order to determine whether the memory cells are programmed or erased, a verify operation is normally performed after the erase and program operation. The verify operation is divided into an overerase verify operation, an erase verify operation, and a program verify operation. The verify operation is identical to a read operation except that the word line voltage used for the read operation is different from that used for the verify operation. For example, a voltage of about 2.8V is applied to a selected word line during an overerase verify operation, a voltage of about 3.5V is applied to the selected word line during an erase verify operation, and a voltage about 6.5V is applied to the selected word line during a program verify operation.
FIG. 5 is a timing diagram for illustrating a verify operation in a conventional flash memory device. Referring to FIG. 5, the verify operation is initiated as the signal VE.sub.-- EN transitions from a logic low level to a logic high level. In particular, the high voltage generator 52 produces the high voltage VPI in response to the low-to-high transition of the signal VE.sub.-- EN. At this time, the PMOS transistor MP1 of the switching circuit 56 is turned on, and the PMOS transistor MP2 is turned off. As the high voltage VPI increases, the voltage VPP regulated by the voltage regulator 54 (hereinafter, referred to as the verify voltage) is transferred via the row selector 20 to the word line WL connected to a selected memory cell. Then, when a sense enable signal SA.sub.-- EN is activated, the sense amplifier 40 detects the threshold voltage of the selected memory cell using a reference voltage from a reference cell to determine whether the selected memory cell is programmed (erased, or overerased) in accordance with the detected result.
As described above, the verify voltages 2.8V, 3.5V and 6.5V for the respective verify operations are derived from the high voltage VPI which is generated by the high voltage generator 52. However, when the high voltage generator 52 produces the high voltage VPI, power supply noise (for example, 10 mV through 50 mV) inevitably arises on the power/ground lines as illustrated in FIG. 5. This causes malfunctions during verify sensing operations in which a fine voltage difference (for example, -30 mV) is detected between a data line DL connected to the memory cell and a reference data line RDL connected to the reference cell. As a result, the threshold voltage of the memory cell deviates from the target threshold voltage distribution, thereby affecting read/program/erase operations which are performed after the above described verify operation.